中圖分類號：TN913 文獻標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.245941
中文引用格式： 史清，蔣海平，姚賽杰，等. 10G以太網(wǎng)的信號處理關(guān)鍵技術(shù)[J]. 電子技術(shù)應(yīng)用，2024，50(12)：1-6.
英文引用格式： Shi Qing，Jiang Haiping，Yao Saijie，et al. Overview on the key technology of signal processing for 10G Ethernet[J]. Application of Electronic Technique，2024，50(12)：1-6.

Overview on the key technology of signal processing for 10G Ethernet

Abstract： With the rapid upgrades of products such as AI PCs, Wi-Fi routers, and GPON, high-speed wired network is an essential part of network infrastructure, Ethernet PHY chips have to provide higher transmission rates to better meet the growing bandwidth demands in the era of big data. 10G Ethernet technology is bound to become the key evolution direction for the next generation of Ethernet. The development of 10G Ethernet PHY chips need to overcome a series of technical challenges, including high-speed signal integrity and low-power design. This paper focuses on the key issues of signal processing in 10G Ethernet PHY chips, firstly introducing the background of relevant international standards for 10G Ethernet, then discussing the network requirements for 10G Ethernet, and next describing the key technologies for signal processing at the physical layer of 10G Ethernet. Finally, the paper makes a summary and outlooks the further development of high-speed Ethernet.

Key words : Ethernet；high-speed data transmission；physical layer technology