中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.257199
中文引用格式： 楊金燁，劉云晶，劉夢影. 高安全性測試數據分層的芯片測試方案設計[J]. 電子技術應用，2026，52(7)：49-52.
英文引用格式： Yang Jinye，Liu Yunjing，Liu Mengying. Design of a chip testing scheme with high security and hierarchical test data[J]. Application of Electronic Technique，2026，52(7)：49-52.

Design of a chip testing scheme with high security and hierarchical test data

Abstract： With the continuous improvement in the integration level and complexity of embedded chips, the bottlenecks of traditional testing methods in terms of security, flexibility, and testing efficiency have become increasingly prominent. Therefore, this paper takes a general-purpose Microcontroller Unit (MCU) as the research object, conducts an in-depth analysis of the core technologies of chip testing modes, and proposes a chip testing scheme that integrates high-security test mode access and hierarchical test data allocation. This scheme achieves secure access to the test mode through a 63-bit key authentication mechanism. Meanwhile, it constructs a hierarchical architecture consisting of IO direct control, register control, and Flash system configuration value control to ensure the flexible allocation of test data. The scheme can fully cover the testing requirements of multiple modules of the chip and provide reliable support for chip testing in high-security scenarios.

Key words : embedded chip testing；test mode；JTAG；key authentication；hierarchical test data