中圖分類號：TN47
文獻標(biāo)志碼：A
DOI: 10.16157/j.issn.0258-7998.223046
中文引用格式： 張曉磊，戴紫彬，郭朋飛，等. 基于RISC-V的AES密碼加速引擎設(shè)計與驗證[J]. 電子技術(shù)應(yīng)用，2023，49(2)：39-44.
英文引用格式： Zhang Xiaolei，Dai Zibin，Guo Pengfei，et al. Design and verification of AES cryptographic acceleration engine based on RISC-V[J]. Application of Electronic Technique，2023，49(2)：39-44.

Design and verification of AES cryptographic acceleration engine based on RISC-V

Abstract： With the rapid development of IoT technology and the widespread deployment of IoT devices, the issue of information security has become increasingly prominent. Cryptography is the key core technology to ensure information security, but the traditional cryptographic algorithm adaptation scheme is difficult to balance performance and flexibility, this paper proposes a cryptographic instruction extension scheme to achieve a good balance between the two scheme. Firstly, we analyze the computational aspects of the AES algorithm, and propose a cryptographic instruction extension and acceleration engine design scheme by combining the Hummingbird E203 processor architecture; then we complete hardware and software implementation, build an RTL-level simulation environment and an FPGA board-level verification environment; finally, we perform experimental verification and comparative analysis. The experimental results show that the proposed scheme can achieve about 700% acceleration ratio with only nearly 2% increase in hardware resources, which has high energy efficiency and can be applied in resource-constrained situations such as IoT.

Key words : RISC-V；cryptographic instruction extension；acceleration engine；information security