中圖分類號： TN913.3
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.211551
中文引用格式： 張立國，李福昆，嚴偉，等. HART調制解調芯片高速通信接口設計[J].電子技術應用，2022，48(4)：6-11.
英文引用格式： Zhang Liguo，Li Fukun，Yan Wei，et al. Interface design of HART modulation and demodulation chip[J]. Application of Electronic Technique，2022，48(4)：6-11.

Interface design of HART modulation and demodulation chip

Abstract： In order to adapt to the current factory equipment, aiming at the huge amount of equipment and data transmission, this paper designs a new HART modulation and demodulation core interface, which uses AXI4 bus interface to replace the traditional UART interface to accelerate the communication speed between HART modulation and demodulation chip and CPU. Compared to the traditional URAT interface, the AXI4 bus interface can transmit 32 bits of 8 bytes in parallel, and the data transfer speed can reach the NS level. Through the interconnection of AXI4 bus module and CPU, the structure function configuration and data interaction are realized. The high-speed communication interface design of HART modulation and demodulation chip was verified based on FPGA platform. The results show that the architecture can effectively identify HART communication protocol, the data interaction between CPU and HART chip reaches NS level, and the correct rate of modulation and demodulation reaches 100%, which meets the requirements of HART communication protocol.

Key words : communication chip architecture；chip interconnection；HART communication protocol；communication interface